1. Field of the Invention
This invention relates to integrated circuit (IC) current mirrors, and more particularly to current mirrors, configured from metal oxide semiconductor field effect transistors (MOSFETs), which include circuitry to maintain the drain voltage on the input transconductance transistor approximately equal to the drain voltage on the output transconductance transistor to provide low current gain error and wide output voltage dynamic range.
2. Description of the Prior Art
Current mirrors are used in ICs to provide an output current which is proportional to an input current. Current mirrors are particularly useful in operational transconductance amplifiers (OTAs). Some complementary metal oxide semiconductor (CMOS) OTAs couple an NMOS current mirror with a PMOS current mirror to provide the output stage of the OTA.
Referring to FIG. 1, a simple (NMOS) current mirror consists of an input transconductance device, FET N1, and an output transconductance device, FET N2. The sources of both transistors are connected to a reference potential, VSS. The drains of both transistors receive current from a common supply voltage (not shown).
The gates of transistors N1 and N2 are connected together and to the drain terminal of the input transconductance device N1. Because no current can flow through the gate terminal of the input transconductance device, all of the input current I.sub.-- IN flows through the input transconductance device drain terminal. The gate terminal voltage of the input transconductance device will rise to the potential needed for the input transconductance device N1 to conduct the input current. Since the gate of the output transconductance device N2 is connected to the same point as the gate of the input transconductance device, the gate-source voltage V.sub.GS of both transistors will be the same, and will vary as a function of the input current I.sub.-- IN. Both the input and output transconductance devices are operated in the saturation region so that the drain current will not significantly vary as a function of the drain supply voltage. If the transistors are matched with respect to threshold voltages, V.sub.T, and width/length (W/L) ratios, the output current I.sub.-- OUT will "mirror" the input current I.sub.-- IN.
When the output of a simple current mirror is used as the output of an operational amplifier, the drain resistance of the output transconductance device is in parallel with the load resistance. The finite resistance of the output transconductance device tends to limit the voltage gain of the amplifier (Av.apprxeq.g.sub.m R.sub.L).
To increase the output resistance of prior art current mirrors, a cascode device is often used in the output stage. FIG. 2 shows the placement of FET N3 as an output cascode device. The gate of the output cascode device N3 is coupled to the gate and drain terminals of a (diode-connected) input cascode device N4, which receives the current input to the mirror. Transistor N3 serves to reduce the voltage swing at the drain of the output transconductance device N2 in relation to the voltage swing at the output of the current mirror. Because the gate voltage of transistors N3 and N4 are equal, the source voltages undergo similar, but not equal variations. When the voltage swing at the drain of the output transconductance device N2 is reduced, the output current consumed by the output resistance of the transconductance device is reduced proportionately. Accordingly, the output current more nearly matches the input current, as compared to the simple current mirror configuration.
Adding an output cascode device to reduce by more than a factor of 10 the drain voltage swing of the output transconductance device significantly reduces the small signal current consumed by the impedance of the output transconductance device. This increases the input to output current matching of the current mirror. The resulting voltage gain of an OTA using such mirrors is increased over that possible using simple mirrors by a substantial factor. That factor is proportional to the reduction in output transconductance device voltage swing compared to the cascode device drain output voltage swing at the signal frequency in question.
The prior art current mirror of FIG. 3 uses an operational amplifier AMP.sub.-- A to control the gate voltage of the output cascode device N3. The non-inverting input of the amplifier is coupled to a reference potential VREF1. The inverting input of the amplifier is coupled to the node connecting the source terminal of the output cascode device N3 and the drain terminal of the output transconductance device N2. The operational amplifier and transistor N3 provide a feedback loop to control the voltage at the drain of the output transconductance device N2. A decrease in the output voltage V.sub.-- OUT results in increased gate potential to transistor N3 which in turn reduces the decrease in the voltage at the drain of transistor N2.
In the current mirrors of FIGS. 2 and 3, a certain minimum voltage drop is required across the cascode output stage to keep it in the high-impedance saturated region of operation. In addition, the source voltage of the cascode output stage must be high enough to maintain the output transconductance device N2 in saturation. Practical minimums for the drain to source voltage drop in CMOS wideband amplifiers have been in the range of 0.3 to 0.5 V. Thus, the output stage of an OTA, using complementary N and P cascode mirrors, consumes a total voltage drop of 4 times 0.3 to 0.5 V, or 1.2 to 2 V. If the voltage supply is 3V, only 1 to 1.8 V is left for output voltage swing. This situation presents a serious problem as supply voltages in CMOS ICs continue to decrease (for example, from 3V to 2.5 V) to accommodate decreasing line-widths (for example from 0.35 to 0.25 .mu.m). As line widths decrease, the maximum drain to source voltage drop of FETs has typically been correspondingly decreased in order to avoid hot electron degradation and excess drain current loss due to impact ionization.
In the prior art circuit of FIG. 4, a diode connected transistor N5 is used to bias the source voltage of cascode transistors N4 and N3 such that the drain voltage of the transconductance devices N1 and N2 will be just above the voltage required to maintain the transconductance devices in saturation. The object is to lower the drain to source voltage drop for the output transconductance device to make more of the supply voltage available for output voltage swing. However, such circuit arrangement has a tendency toward non-linear operation. Because the output transconductance device N2 is biased close to the edge of saturation, a drop in the output voltage V.sub.-- OUT which is sufficient to cause the output cascode device N3 to drop out of saturation will in turn cause the output transconductance device N2 to drop out of saturation. Thus, the input transconductance device N1 may be operating in saturation, while the output transconductance device N2 is operating below saturation, resulting in non-linear operation.
Combining the techniques of the FIGS. 3 and 4 circuits does not overcome the deficiencies of conventional current mirrors. For example, utilizing an operational amplifier as shown in FIG. 3 to stabilize the source voltage of the output cascode device N3 of FIG. 4 provides only a small improvement in output voltage swing. This is because the key to the FIG. 4 circuit is to place the source voltage of the output cascode device N3 close to the voltage corresponding to the edge of saturation for the output transconductance device N2. Therefore, output voltage swings slightly larger than those required to keep the output cascode device N3 in saturation, in turn cause the output transconductance device N2 to drop out of saturation, thereby not overcoming the resultant potential for non-linear operation.
Using the wide-swing biasing technique of FIG. 4 to place the drain voltage of the transconductance device N2 close to the edge of saturation in the current mirror of FIG. 3 increases transient response problems known to exist in the current mirror of FIG. 3. When a dip in the output voltage V.sub.-- OUT causes the cascode device N3 (of FIG. 3) to drop out of saturation, a large gate control voltage is generated by the operational amplifier. The time required for removal of the large gate control voltage induces output transients when the output cascode device returns to the saturation mode of operation.